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DLXview
Interactive visual pipeline simulator using DLX instruction set; operation of pipelined processor is easier to understand than trying to imagine operation from text descriptions; modified and extended from DLXsim. Documents, downloads.
http://cobweb.ecn.purdue.edu/~teamaaa/dlxview/
Purdue.edu ~
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DLX Implementation at MSU
Documents DLX implementation by Microsystems Prototyping Laboratory (MPL), MSU Engineering Research Center; used as design driver to help validate standard cell libraries.
http://www.hpc.msstate.edu/mpl/education/docs/dlx/
Msstate.edu ~
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DLX Simulation Tools
Set of tools to build and simulate programs to run on DLX architecture, for exploring an operating system (DLXOS) in a simulated environment. Overview, architecture, OS, simulator, debugger, instructions.
http://www2.ucsc.edu/courses/cmps111-elm/dlx/
Ucsc.edu ~
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ASPIDA Project
ASynchronous, open source, Processor IP of the DLX Architecture. Goal: show feasibility to design and deliver asynchronous open IPs in portable, re-usable way. Information, downloads. Open source hardware.
http://www.ics.forth.gr/carv/aspida/
Forth.gr ~
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DLX in VHDL
VHDL model of processor; most instructions use 5 clock cycles to run, jumps use 3, floating point timing not fully accurate because fp instructions also take 5 cycles to run; description, download.
http://www.cse.lehigh.edu/~caar/lou/dlx.html
Lehigh.edu ~
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