Verilog

Free Model Foundry
This is the premier site for VHDL and Verilog component simulation models.
Freemodelfoundry.com ~

Similar Sites: freemodelfoundry.org

Arduino, Boarduino, AVR, układy programowalne, FPGA, CPLD, Verilog • Mikrokontroler.info
Znajdziesz tu tutoriale, opisy, porady dotyczące różnych rodzin mikrokontrolerów (AVR, ARM). Dowiesz się co nie co o platformie Arduino oraz o układach programowalnych i elektronice.
Mikrokontroler.info ~

DefineView Consulting - Home
DefineView Consulting offers a comprehensive System Verilog Assertions (SVA) and Functional Coverage Language and methodology training class using real life applications and LABs including a Reference Grade Training Book. Taught by seasoned engineers.
Defineview.com ~

Clock to Q
A complete VLSI reference
Clocktoq.com ~

Similar Sites: vlsiworld.com

Robei
Simplify Hardware Design
Robei.com ~

Verilog code to implement clock domain crossing, rate change asynchronous fifo depth calculation, half-adder, full-adder, tristate buffer, binary to gray conversion, $readmemh, file read write, $display, $fdisplay, $random, testbench. Python glob.glob module, sys.argv, commandline, stripoff, classes and global variable. 2,3 ,4 ,5 variable Karnaugh k-map tutorial, xor, xnor gate truth-table,Boolean Algebra, Duality Principle, Huntington Postulates, Canonical and Standard Forms, Minterms and Maxterms, SOM, Prime Implicant and Gate level minimization.
Verilog code for clock domain crossing, rate change fifo design or asynchronous fifo depth calculation, binary to gray conversion, file read write $display/$fdisplay, $readmemh functions, half-adder, full-adder, tri-state buffer and testbenches. Python scripts file read write, glob.glob module, hex to signed . Overflow, magnitude/integer conversion, sys.argv/commandline arguments, generate diamond pattern, stripoff white space, classes and global variale. Digital Basics tutorial with examples - Binary numbers, 1s and 2s complement, Binary arithmetic, Signed Magnitude, Gray coding, BCD coding/addition, Digital logic gates, Boolean Algebra, Duality Principle, Huntington Postulates, Theorems, Canonical and Standard Forms, Minterms and Maxterms, SOM, POM or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s , Prime Implicant and Gate level minimization examples. enable/disable counter, python error handling typeerror, attributeerror. RTL coding guidelines, guide to graduate studies and interview questions RF tutorial - SignaltoNoise(SNR), NoiseFactor(F), NoiseFigure(NF),Dynamic Range (DR), Minimum Detectable Signal (MDS), Intermodulation (IM) distortion, Second order (IP2) & Third order (IP3) intermodulation products, IP3 (Third Order Intercept) plot,Desensitization, Cross-modulation, Spurious outputs, Gain control, Noise.
Fullchipdesign.com ~

Programall Technologies Inc
HARDWARE AND SOFTWARE DESIGN SERVICES
Programall.com ~

HDL Works: HDL Design Entry and Verification Tools
HDL Works - Front-End HDL Entry Tools EASE, HDL Companion, IO Checker.
Hdlworks.com ~

Similar Sites: iochecker.com - translogiccorp.com

Sarge's Invincible Consulting: An ASIC architecture, digital design, and verification consultant engineer based in Austin, TX, specializing in rtl, specman, and verilog
ASIC FPGA consultant architect digital design verification engineer rtl verilog specman Austin TX Texas resume
Kavcak.com ~

글로닉스 - Welcome to Glonix
FPGA, verilog, vhdl, PCI, USB, AVR, ATmega
Glonix.com ~

Similar Sites: smart-contacts.com