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Gaisler Research AB
Provides IP cores, supporting development tools for embedded processors based on SPARC architecture. Key product: LEON synthesizable processor model, full development environment, and library of IP cores, GRLIB. Göteborg, Sweden.
http://www.gaisler.com/cms4_5_3/
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LEON2FT Notes
Functional SPARC compatible processor core. Fault tolerant version of LEON2, derived from LEON-1 integer unit, implemented as highly configurable, synthesizable VHDL model. Runs on Altera, Mietec, Temic MG2, Xilinx. Designed for outer space uses. Open so
http://microelectronics.esa.int/core/ipdoc/leon2ft_notes.txt
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OpenSPARC.net
Sun Microsystems initiative to create open source community and participation in processor architecture development; news, documents, analysis, downloads.
http://www.opensparc.net/
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Simply RISC
Designs and supports open-source RISC processors, systems, peripherals; sells S1 Core, a 64-bit Wishbone-compliant CPU Core based on reduced Sun Microsystems OpenSPARC T1 microprocessor. Catania, Italy; Bristol, UK.
http://www.srisc.com/
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OpenSPARC T1
Open source version of UltraSPARC T1 processor, with CoolThreads technology; high throughput, low power, for high performance per watt; 32 simultaneous processing threads, uses about as much power as a light bulb. SunSource.net.
http://opensparc-t1.sunsource.net/
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S1 Core
This core (codename Sirocco) is one 64-bit core from the OpenSPARC T1 8 core processor (codename Niagara), plus a Wishbone bridge, reset controller, and basic interrupt controller, to make it easy for engineers to integrate the design. SunSource.net.
http://s1.sunsource.net/
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